(1) Field of the Invention
The present invention relates to a semiconductor integrated circuit. More particularly, the present invention relates to the power supply path for a semiconductor integrated circuit.
(2) Description of the Prior Art
FIG. 1 is a circuit diagram illustrating the structure of a memory cell of a static memory comprising an insulated gate field effect transistor (hereinafter referred to as "MOS transistor"), which is one example of a conventional semiconductor integrated circuit. The memory cell circuit shown in FIG. 1 comprises as a main member a flip-flop circuit in which a polycrystalline silicon layer of a high resistivity of 10.sup.10 to 10.sup.12 .OMEGA. is used as the load resistance. Referring to FIG. 1, the memory cell comprises MOS transistors T1 and T2 for switching the flip-flop circuit, resistances R1 and R2 for supplying a current to the MOS transistors T1 and T2 from a power supply line 1, a ground line 2 connected to sources of the MOS transistors T1 and T2, gate-switching transistors T3 and T4 connecting data lines 3 and 4 to the flip-flop and a word line 5 connected to gates of the MOS transistors T3 and T4. In the conventional cell where polycrystalline silicon layers of a high resistivity of 10.sup.10 to 10.sup.12 .OMEGA. are used as the resistances R1 and R2, as shown in FIG. 2, a polycrystalline silicon layer 8 (i-layer) of a high resistivity is formed over a silicon substrate 6 on an SiO.sub.2 film 7, and one end of this layer 8 is connected to a predetermined region of substrate 6 through a layer 9 of the n.sup.+ type and the other end of the layer 8 is connected to a power supply line 1 through a layer of the n.sup.+ type. By virture of a current flowing through the high-resistivity polycrystalline layer 8, destruction of memory information by leakage currents of the MOS transistors T1 and T2 shown in FIG. 1 is prevented. In the conventional memory cell shown in FIG. 1, there are one power supply line, one ground line, a total of two data lines and one word line, that is, five lines. Disposition of these many lines results in an increase in the area of the memory cell and is not preferred from the viewpoint of packing density. Furthermore, the presence of the high-resistivity polycrystalline silicon layer is another cause of an increase in the area of the memory cell.